I. Field
The present invention relates generally to electronic circuits, and more specifically to metal oxide semiconductor (MOS) circuits.
II. Background
Integrated circuit (IC) fabrication technology continually improves and, as a result, the size of transistors continues to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller IC die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
For complementary metal oxide semiconductor (CMOS), which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is leakage current. Smaller geometry for a transistor results in higher electric field, which stresses the transistor and causes oxide breakdown. To decrease the electric field, a lower power supply voltage may be used for the smaller geometry transistor. Unfortunately, the lower power supply voltage also increases the delay of the transistor, which is undesirable for a high-speed circuit. To reduce the delay and improve operating speed, the threshold voltage (Vt) of the transistor may be reduced. The threshold voltage is the voltage at which the transistor turn on. However, the lower threshold voltage and smaller geometry result in higher leakage current, which is the current passing through the transistor when it is turned off.
Leakage current is more problematic as CMOS technology scales smaller. This is because leakage current increases at a high rate with respect to the decrease in transistor size. Leakage current is also more problematic for certain applications such as portable devices, e.g., cellular phones and laptop computers. Leakage current consumes battery power and reduces standby time for portable devices that use internal batteries.
Reducing leakage current without sacrificing too much performance is a major challenge in CMOS designs, especially as IC technology scales down to 90 nm (nanometer) and smaller. A CMOS circuit that is constructed entirely using high threshold (HVT) transistors has low leakage current but is also slow. A CMOS circuit that is constructed entirely using low threshold (LVT) transistors is faster but has high leakage current.
There is therefore a need in the art for CMOS circuits having good performance and low leakage current.